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HZU6.8Z
Silicon Epitaxial Planar Zener Diode for Surge Absorb
REJ03G1219-0200 (Previous: ADE-208-777A) Rev.2.00 Jun 16, 2005
Features
* Low capacitance (C = 25 pF max) and can protect signal line from ESD. * Ultra small Resin Package (URP) is suitable for surface mount design.
Ordering Information
Type No. HZU6.8Z Laser Mark 68Z Package Name URP Package Code (Previous Code) PTSP0002ZA-A (URP)
Pin Arrangement
Cathode mark Mark 1
68Z
2 1. Cathode 2. Anode
Rev.2.00 Jun 16, 2005 page 1 of 5
HZU6.8Z
Absolute Maximum Ratings
(Ta = 25C)
Item Power dissipation Junction temperature Storage temperature Note: See Fig.2. Symbol Pd * Tj Tstg Value 200 150 -55 to +150 Unit mW C C
Electrical Characteristics
(Ta = 25C)
Item Zener voltage Reverse current Capacitance Dynamic resistance ESD-Capability * Symbol VZ IR C rd -- Min 6.47 -- -- -- 20 Typ -- -- -- -- -- Max 7.0 2 25 30 -- Unit V A pF kV Test Condition IZ = 5 mA, 40 ms pulse VR = 3.5 V VR = 0 V, f = 1 MHz IZ = 5 mA C = 150 pF, R = 330 , Both forward and reverse direction 10 pulse
Note: Failure criterion ; IR > 2 A at VR = 3.5 V.
Rev.2.00 Jun 16, 2005 page 2 of 5
HZU6.8Z
Main Characteristic
10-2 250
Polyimide board 20hx15wx0.8t
10-3
Zener Current IZ (A)
Power Dissipation Pd (mW)
200
3.0
1.5
150
1.5
unit: mm
10-4
100
10-5
50
10-6
0
2
4
6
8
10
0
0
50
100
150
Zener Voltage VZ (V) Fig.1 Zener current vs. Zener voltage
Ambient Temperature Ta (C) Fig.2 Power Dissipation vs. Ambient Temperature
Nonrepetitive Surge Reverses Power PRSM (W)
104 PRSM t 10
3
Ta = 25C nonrepetitive
102
10
1.0
10-5
10-4
10-3 Time t (s)
10-2
10-1
1.0
Fig.3 Surge Reverse Power Ratings
Rev.2.00 Jun 16, 2005 page 3 of 5
0.8
200
HZU6.8Z
104
Transient Thermal Impedance Zth (C/W)
103
102
10
1.0
10-2
10-1
1.0 Time t (s)
10
102
103
Fig.4 Transient Thermal Impedance
Rev.2.00 Jun 16, 2005 page 4 of 5
HZU6.8Z
Package Dimensions
JEITA Package Code SC-76A RENESAS Code PTSP0002ZA-A Previous Code URP / URPV MASS[Typ.] 0.004g
D b
E HE
l1 e1 A2 l1 b2
Pattern of terminal position areas
Reference
Dimension in Millimeters
Symbol
A1
A1 A2 b D E HE b2 e1 l1
Min 0 0.75 0.15 1.10 1.55 2.35 -
Nom 0.90 0.30 1.25 1.70 2.50 0.80 2.30 0.80
Max 0.1 1.05 0.45 1.40 1.85 2.65 -
Rev.2.00 Jun 16, 2005 page 5 of 5
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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http://www.renesas.com
(c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
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